Semiconductor memory having a dynamic level detecting means for detecting a level of a word line
US4719603A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Apr 15, 1986 |
| Grant date | Jan 12, 1988 |
| Priority date | — |
| Expiry date | Apr 15, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory includes a word line driving circuit whose output terminal is coupled to one end of each word line of a memory array, and also an auxiliary driving circuit which drives the other end of the word line upon receiving a selection signal transmitted to the other end of this word line. The auxiliary driving circuit comprises a level detector circuit which is dynamically driven by a timing signal, and a driving element which is driven by an output of the level detector circuit to drive the other end of the word line. When the word line is to be reset, the output of the level detector circuit is set at a level which brings the driving element into an "off" state. The auxiliary driving circuit of this arrangement permits the other end of the word line to change to a selection level quickly and to be reset quickly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.