Frequency locked loop with constant loop gain and frequency difference detector therefor
US4720687A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 1987 |
| Grant date | Jan 19, 1988 |
| Priority date | — |
| Expiry date | Feb 20, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/087
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital signal regenerator comprises a quantizer, a sampler, a timing extractor and a frequency and phase locked loop. The included frequency locked loop employs a frequency difference detector and a frequency generator which it shares with the included phase locked loop. The frequency difference detector includes flip-flops for generating square wave frequency difference signals, obviating the need for the multipliers, comprators and low pass filters used in prior devices. In addition, the frequency difference detector includes pulse-width modulator which is controlled by a pulse-width regulator. The regulator provides for a constant loop gain for the frequency locked loop over different reference frequencies output by the frequency generator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.