Hybrid floating point/logarithmic number system arithmetic processor
US4720809A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 21, 1984 |
| Grant date | Jan 19, 1988 |
| Priority date | — |
| Expiry date | Sep 21, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5235
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hybrid arithmetic processor which combines attributes of conventional floating point (F.P) arithmetic with logarithmic number system (LNS) arithmetic. The arithmetic processor includes an input section (forward code converter) for converting input operands in F.P. format to intermediate operands in LNS format, an LNS arithmetic section for performing an arithmetic operation on the LNS intermediate operands and providing an intermediate output in LNS format, and an output section (inverse code converter) for converting the LNS intermediate output to an output in F.P. format. Significantly, output is provided in normalized floating point format but without the need for a time-consuming exponent alignment operation. Arithmetic operations, including addition and multiplication, are accomplished at a high speed, which speed moreover is constant and independent of the data. An efficient accumulator structure and the structure of an ultra-fast numeric processor are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.