Semiconductor memory device in form of shift register with two-phase clock signal supply
US4720815A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 19, 1986 |
| Grant date | Jan 19, 1988 |
| Priority date | — |
| Expiry date | May 19, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/184
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device in the form of a shift register is supplied with two-phase clock signals. One of the two-phase clock signal lines is connected to even order shift register elements of the shift register, and the other of the two-phase clock signal lines is connected to odd order shift register elements of the shift register. Each of the shift register elements includes an output node, a gate connected between the output node and a clock signal supplying node, a charge-up circuit responsive to the output signal of the preceding shift register element for preliminarily charging a control node of the gate, and a discharge circuit responsive to the output of the succeeding shift register element for releasing the charge of the control node of the gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.