Single layer poly fabrication method and device with shallow emitter/base junctions and optimized channel stopper
US4721685A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 1986 |
| Grant date | Jan 26, 1988 |
| Priority date | — |
| Expiry date | Apr 18, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76216
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating high performance bipolar transistors using a single polycrystalline silicon layer whereby horizontally and vertically scaled base/emitter junctions are achieved. In an extrinsic base transistor, a composite sandwich of overlying layers of poly silicon, oxide and nitride are deposited over a substrate containing field oxide isolated monocrystalline transistor sites having buried subcollectors and sinker regions. The composite sandwich is thereafter selectively oxidized to define base, emitter and collector regions with the relative thickness of the composite sandwich and the grown oxide being controlled to assure proper horizontal extrinsic base to emitter spacings and shallow vertical intrinsic base to emitter junctions, upon completing subsequent implant and annealing steps. Each active transistor site is also surrounded by a ring-like, channel stopper which is physically isolated from the channel stopper of each other device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.