Method and apparatus for implementing modulo arithmetic calculations
US4722067A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 25, 1985 |
| Grant date | Jan 26, 1988 |
| Priority date | — |
| Expiry date | Mar 25, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/106
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A modulo arithmetic unit and method for providing a sum of first and second numbers is provided. In one form, a first adder calculates a first sum which is equal to the arithmetic sum of the first and second numbers. A second adder is provided for adding the first number to an offset value equal to (2.sup.X -M), where X defines the number of bits of the number system used, M is a predetermined modulus and X and M are integers. A third adder operates in parallel with the first adder to calculate the sum of the output value of the second adder and the second operand to provide a second output sum and a carry output bit. In another form, only two adders are utilized wherein the first adder calculates a first output sum of the first and second numbers, and the second adder calculates the sum of the first output sum and the offset value. Both illustrated forms utilize a multiplexer which outputs one of the two calculated output sums depending upon whether a wraparound of an upper modulus boundary occurred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.