Digital adaptive voting
US4723242A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 1986 |
| Grant date | Feb 2, 1988 |
| Priority date | — |
| Expiry date | Jun 27, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/183
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital system employing adaptive voting circuitry to improve its fault-tolerance receives an input data bit from each of a number of input data sources. The adaptive voting circuitry has a separate section for each of the input devices which has a weight register that stores an initial weight value which determines the voting strength of the associated input device. The weight values are multiplexed through to a voting circuit which also receives the input data bits. If an input data bit is a logic "1" the weight value of the input data device that supplied this "1" signal is added to the weight values of all other input data devices that supplied "1" data bits. If the data bit from a particular input device is a logic "0", then its weight is added to the weight values for other input data devices which supplied logic "0'". Accumulative voting then takes place via adders in the voting circuit which determines whether the correct output bit should be a logic "1" or a logic "0". After the correct output bit is obtained, it is compared with the input bits supplied by the different input data devices, and the stoned weight values associated with each of these are decremented if the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.