Method of forming a semiconductor device having several gate levels
US4724218A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 1986 |
| Grant date | Feb 9, 1988 |
| Priority date | — |
| Expiry date | Jun 12, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D44/041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a method for forming a semiconductor device having several gate levels, which, in the case of forming a device with two gate levels, comprises the following steps: PA0 1. on a semiconductor substrate are deposited a dielectric layer, then a layer of material in which the gates of the first level are to be formed and a dielectric layer; PA0 2. the gates of the first level are formed by etching the two upper layers; PA0 3. the sides of the gates of the first level are isolated; PA0 4. a second layer is deposited of material in which the gates of the second level are to be formed; PA0 5. in this second layer an opening is formed giving access to the dielectric layer covering the top of the gates of the first level; PA0 6. by plasma etching or by chemical etching the zones of said second layer which overhang the gates of the first layer are removed by etching them simultaneously on their internal and external faces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.