Bi-MOS PLA
US4725745A · kind A · utility
7Cited by
0References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 22, 1984 |
| Grant date | Feb 16, 1988 |
| Priority date | — |
| Expiry date | Aug 22, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated programmable logic array formed within a single silicon chip comprises a combination of a logical product gate array and a logical summation gate array. The logical product gate array is equipped with a plurality of MIS field-effect transistors whose gates are selectively driven by a plurality of input signals. Source-drain paths of these transistors are connected in series. The logical summation gate array is equipped with a plurality of inverted bipolar transistors having collector-emitter paths which are connected in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.