Integrated circuit distributed geometry to reduce switching noise
US4725747A · kind A · utility
44Cited by
2References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 1986 |
| Grant date | Feb 16, 1988 |
| Priority date | — |
| Expiry date | Aug 29, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/122
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A complimentary output pair (10) having a P-channel transistor (12) and an N-channel transistor (14) prevents output voltage spikes due to rapid changes in current with respect to time at the V.sub.cc power supply and ground (32) nodes by using a "graded turn-on." Both the P-channel transistor (12) and the N-channel (14) utilize a serpentine polysilicon gate (16), (24), in order to sequentially turn on the sub-transistors in response to a changing input. Pull-up (36) and pull-down (40) transistors are used to turn the sub-transistors (21a-j, 29a-f) off simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.