Architecture for a fast frame store using dynamic RAMS
US4725987A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 23, 1985 |
| Grant date | Feb 16, 1988 |
| Priority date | — |
| Expiry date | Oct 23, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fast frame store incorporating a memory array having selectable memory banks which include a plurality of relatively slow dynamic RAMs (DRAMs) is disclosed. The frame store has a buffered input and a buffered output to slow the data rate. Data can be read in parallel into a selected memory bank while at the same time other data are being read in parallel out of another selected memory bank. Refresh of DRAMs of an unselected bank occurs simultaneously with the transfer of data to or from the frame store. Several memory banks of the frame store are connected to a single row address select (RAS) line, so that when a selected bank is being addressed for data transfer, the memory location of several other unselected banks are being refreshed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.