LSI gate array having reduced switching noise
US4727266A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 1987 |
| Grant date | Feb 23, 1988 |
| Priority date | — |
| Expiry date | Feb 24, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
As the number of output circuit increases in LSI or VLSI circuit, there increases the chance of many large output circuits operates at a same instant, and it causes malfunction of logic by induced switching noise. In order to prevent such problem, the switching speed of driving buffer circuit for output buffer circuit is controlled. By reducing the switching capacity of the driving circuit, the switching speed of the total circuit is not affected so much, but the noise is decreased very much. The control of the switching capacity of the driving buffer circuit is performed by master slice technology. Such as perfectly opposite design concept to that of present LSI design has been proofed by experiments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.