Staging memory for massively parallel processor
US4727474A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 18, 1983 |
| Grant date | Feb 23, 1988 |
| Priority date | — |
| Expiry date | Feb 18, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention herein relates to a computer organization capable of rapidly processing extremely large volumes of data. A staging memory is provided having a main stager portion consisting of a large number of memory banks which are accessed in parallel to receive, store, and transfer data words simultaneous with each other. Substager portions interconnect with the main stager portion to match input and output data formats with the data format of the main stager portion. An address generator is coded for accessing the data banks for receiving or transferring the appropriate words. Input and output permutation networks arrange the lineal order of data into and out of the memory banks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.