Power buffer circuit
US4728901A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 7, 1986 |
| Grant date | Mar 1, 1988 |
| Priority date | — |
| Expiry date | Apr 7, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/505
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power buffer circuit includes a power MOS device connected via a local feedback loop to a differential amplifier. The MOS device amplifies the power of an input signal to produce an output signal. The differential amplifier causes the output signal voltage to follow the input signal voltage by sensing a difference between the two voltages and generating in response a difference signal to the MOS device to change the output signal voltage level. The buffer circuit may be configured as a current source or a current sink that maintains unity voltage gain from the input to output signal. The power buffer circuit may be incorporated into a voltage regulator that maintains a remotely sensed output voltage substantially equal to a predetermined factor of a reference voltage via a second, outer feedback loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.