Method and apparatus for extracting a predetermined bit pattern from a serial bit stream
US4730346A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 12, 1987 |
| Grant date | Mar 8, 1988 |
| Priority date | — |
| Expiry date | Feb 12, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0605
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An embedded framing bit pattern in a serial bit stream is located by combining the last bit to arrive of the serial bit stream with a predetermined number of prior bits of the serial bit stream which are spaced apart by the pitch of the bits of the framing bit pattern, and this combination of bits is tested to determine if the combination matches part of the framing bit pattern. If a match does not occur, then the bits which were combined together are changed to a bit pattern that will not result in a match when these bits (except for the eldest bit which is disregarded) is combined again with a new bit of the serial bit stream, no matter what the logic state of the new bit. In this manner all of the bits, as they arrive and are combined and tested, will eventually be changed except the bits which are part of the framing bit pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.