Process for manufacturing metal-semiconductor field-effect transistors

US4731339A · kind A · utility

Assignee

• Rockwell International Corporation · US

Inventors

• Frank Ryan · Cork, IE
• Man-Chung F. Chang · Thousand Oaks, US
• Dennis A. Williams · Colorado Springs, US
• Richard P. Vahrenkamp · Camarillo, US

Key dates

• Filing date: Aug 25, 1986
• Grant date: Mar 15, 1988
• Expiry date: Aug 25, 2006

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0614

Abstract

A single-level photoresist process is used to make metal-semiconductor field-effect transistors (MESFETs) having more uniform threshold voltages. An N.sup.- layer is formed in a semi-insulating semiconductor, followed by formation of a dummy gate using a single-level photoresist process. Using the dummy gate as a mask, ions are implanted to form an N.sup.+ region. The length of the dummy gate is then reduced by plasma etching. A dielectric is deposited over the N.sup.+ region, the N.sup.+ /N.sup.- interface, and the exposed portion of the N.sup.- layer. The dummy gate is lifted off to define a self-aligned, submicron gate opening. The gate opening on the N.sup.- layer is reactive ion etched to obtain the desired threshold voltage, and covered with a Schottky gate metal deposit.