Logic-circuit layout for large-scale integrated circuits
US4731643A · kind A · utility
22Cited by
4References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 21, 1985 |
| Grant date | Mar 15, 1988 |
| Priority date | — |
| Expiry date | Oct 21, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A VLSI chip has multiple annular rings of circuit cells, interspersed with annular wiring channels for interconnecting the cells. Another wiring layer runs perpendicular to the rings. A central chip area contains all the I/O connections for the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.