CMOS output circuit
US4733105A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 1986 |
| Grant date | Mar 22, 1988 |
| Priority date | — |
| Expiry date | Aug 27, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/023
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS output circuit including CMOS inverters, is formed on a semiconductor substrate and N MOS switching transistors are provided. The output circuit is responsive to an external control signal for switching a plurality of reference voltages and delivering them as multiple-level drive signals. The CMOS output circuit furthermore includes PMOS switching circuits connected in parallel with each of a plurality of CMOS transfer gates, CMOS inverters, and N MOS switching transistors for preventing a latch-up phenomenon of the CMOS inverters from being produced. The PMOS switching circuits are on-off controlled by a control signal obtained by converting an amplitude level of an external control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.