BICMOS logical circuits
US4733110A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 1987 |
| Grant date | Mar 22, 1988 |
| Priority date | — |
| Expiry date | Mar 23, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09448
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Logical NAND circuits, each consisting of a logical operational portion, an output control portion comprising the combination of a bipolar transistor and a plurality of NMOS transistors, and an output portion comprising first and second bipolar transistors connected in series between power supply voltage and the ground in which the merits of the MOS transistors and the bipolar transistors can be demonstrated by the particular combination of the two different kinds of the transistors in the logical circuit, thereby increasing the current driving performance while reducing power consumption without making the size of the logical circuit large.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.