Extended range phaselocked loop
US4733197A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 19, 1987 |
| Grant date | Mar 22, 1988 |
| Priority date | — |
| Expiry date | Feb 19, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/199
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An acquisition circuit in an improved phaselocked loop prevents cycle slipping by detecting and compensating an impending large phase difference between an independent incoming signal and a local comparison signal dependently related to a voltage controlled oscillator. A train of pulses is generated in progressively delayed phase relation with each cycle of the oscillator output signal. Additionally a threshold signal related to the independent signal is produced. In response to overlap of the threshold signal and individual ones of the pulses, a phase error signal is generated which controls a commutator to select individual ones of the pulses having a predetermined delay as the comparison signal, thereby generating a correcting control signal to phaselock the oscillator at a faster rate than the linear response time of a standard loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.