Contact vias in semiconductor devices
US4733291A · kind A · utility
5Cited by
4References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 15, 1985 |
| Grant date | Mar 22, 1988 |
| Priority date | — |
| Expiry date | Nov 15, 2005 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/133
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A glass reflow step to round off sharp edges of contact vias is typically included in processes for making integrated-circuit devices. In the course of making such devices with closely spaced vias, it has been found that unacceptable overhangs occur on the sidewalls of the vias. Neither changes in the composition of the glass nor modifications in the processing parameters of reflow were effective to avoid the overhang phenomenon. In accordance with the invention, it has been discovered that the overhang problem can be consistently avoided if the ratio of glass thickness to via-to-via spacing is about .ltoreq.0.393.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.