Semiconductor memory device having serial data input circuit and serial data output circuit
US4733376A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 15, 1985 |
| Grant date | Mar 22, 1988 |
| Priority date | — |
| Expiry date | Oct 15, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device including a memory cell array 1, a serial data input circuit for high-speed, large data store in memory cells and a serial data output circuit for high-speed, large data read-out from the memory cells. The serial data input circuit includes a plurality of shift registers 15, for consecutively storing serial input data S.sub.IN applied from an external circuit, and a plurality of first gates 14, for operatively and simultaneously connnecting the shift registers and a plurality of bit lines BL of the memory cell array to store simultaneously the serial input data stored in the shift registers into desired memory cells selected by a desired word line. The serial data output circuit includes a plurality of second gates 12 operatively connected to the bit lines, a plurality of data holding circuits 7, an input of each being operatively connectable to the corresponding bit line through the corresponding one of the second gates, a plurality of third gates provided between outputs of the data holding circuits and data bus(es) 26 and for outputting data held in the data holding circuits to the data bus(es), and a data output circuit 9, 10 having a gate driving …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.