Readout circuit for dual-gate CID imagers with charge sharing corrected for subtractive error
US4734583A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 1986 |
| Grant date | Mar 29, 1988 |
| Priority date | — |
| Expiry date | Oct 16, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/1575
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A readout circuit for IR sensing charge injection devices (CID) is disclosed, the CID comprising a two-dimensional array of dual-gate sensing sites on an InSb or HgCdTe substrate. The novel readout circuit, which operates in the charge sharing mode (CSM) in extracting image information, is modified to correct for the subtractive effect present when the CSM mode is used. The readout circuit includes a plurality of processors, one for each column, from which a single serial output may be obtained by a demultiplexer, and into which signals derived from successive pixel sites on the associated column are coupled. A first quantity representing the subtractive error is obtained without injection from each column line by double sampling during a first interval. A second quantity representing the signal corrected for subtractive error is obtained with injection from a pixel site by double sampling during a second interval, the samples being increased by the error quantity. The subtractive error compensation may be applied in cases involving either unsaturated or saturated signal fields.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.