CMOS inverter chain

US4734597A · kind A · utility

Assignee

• Intermetall, Division of Ditti · DE

Inventors

• Manfred Ullrich · Bensberg, DE
• Arnold Uhlenhoff · Emmendingen, DE

Key dates

• Filing date: Dec 5, 1986
• Grant date: Mar 29, 1988
• Expiry date: Dec 5, 2006

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03L1/00
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A CMOS inverter chain includes the alternating series connection of N- and P-inverters. An N-inverter is a conventional type of CMOS inverter employing an N-intermediate transistor between both the P- and the N-transistor; a P-inverter, however, is a CMOS inverter employing a P-intermediate transistor between both the P- and the N-transistor. The gates of the intermediate transistors are interconnected and controlled by the clock signal, whereas the inverter input is constituted by the interconnected gates of the P- and the N-transistor of each inverter. Such an inverter chain can be used, for example, as a digital pulse width discriminator, as a final position counter, as a circuit for compensating signal drop-outs in input pulses, or else for effecting ring oscillator synchronizations.