Semiconductor mesa contact with low parasitic capacitance and resistance
US4734749A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 7, 1981 |
| Grant date | Mar 29, 1988 |
| Priority date | — |
| Expiry date | Apr 7, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Method of manufacturing silicon mesa diodes from a wafer of silicon. The surface of the wafer is coated with a first layer of silicon nitride and a second layer of silicon oxide. By masking and etching procedures, silicon nitride is left only on the portions of the surface defining the mesas to be formed. The wafer is etched to form the mesas and then treated to form a passivating silicon oxide coating at all the exposed surfaces of the wafer. The silicon nitride is removed from the upper surfaces of the mesas and metal contacts are applied to these upper surfaces. The wafer is subsequently divided into discrete dice, each containing a mesa, and the dice are mounted in suitable enclosures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.