High speed trunk interface with concurrent protocol handlers
US4734908A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 31, 1986 |
| Grant date | Mar 29, 1988 |
| Priority date | — |
| Expiry date | Oct 31, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/64
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital trunk interface utilizing the first protocol handler to signal the start of a packet and a second protocol handler responsive to the packet delayed to initiate the storage of the packet internally to the digital trunk interface. The digital trunk interface comprises a microprocessor and two universal synchronous asynchronous receiver transmitter (USART) circuits. One USART is directly connected to the incoming digital trunk and is utilized to inform the microprocessor when a packet is first received. The second USART receives the packet delayed by a predefined amount of time from the digital trunk. The microprocessor is responsive to the signal from the first USART that a packet has been received to perform the necessary administrative functions for receipt of the packet by the second USART.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.