FET for high reverse bias voltage and geometrical design for low on resistance
US4735914A · kind A · utility
21Cited by
13References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 8, 1986 |
| Grant date | Apr 5, 1988 |
| Priority date | — |
| Expiry date | Aug 8, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Field-effect transistor devices are provided having a relatively substantial capability to withstand reverse bias voltages. This capability is provided through providing shields in these devices near junctions in such devices which are subject to breakdown under large reverse bias voltages, these shields being operable at selected voltages. The device can also be provided having a relatively low "on" condition resistance between the source and drain terminals thereof by virtue of a geometrical design choice. A method for fabricating one such device is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.