Dynamic CMOS current surge control
US4736119A · kind A · utility
10Cited by
9References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 4, 1987 |
| Grant date | Apr 5, 1988 |
| Priority date | — |
| Expiry date | Feb 4, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0008
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Integrated circuits having a large number of transmission gate logic stages have been found to draw a large current surge on power-up. This is due to the floating input node of complementary inverters causing current to flow briefly before clock pulses arrive. The present invention provides a DC voltage on the gates of the pass transistors until the system clock pulses arrive, thereby eliminating the floating node. An optional periodic window may be generated to examine the system clock after power-up, to detect a loss of clock condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.