Electronic data processing system overlaid jump mechanism
US4736292A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1985 |
| Grant date | Apr 5, 1988 |
| Priority date | — |
| Expiry date | Dec 16, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/264
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A series of instructions N, N+1, N+2, etc. are issued by an instruction buffer 14 at a fixed clock rate in a pipelined method to parallel instruction flow path 6 and control word flow path 8, each path including a serial coupled holding register 20, 21, an instruction register 18, 19 and a function register 16, 17. If instruction N is a jump instruction, it and the related control word, when stored in the function registers 16, 17 causes the jump target instruction and the related control word of the jump instruction N to be entered into the holding register 20, 21. If the jump instruction N jump conditions are satisfied, the jump target instruction and related control word are written into the instruction registers 18, 19 and then into the function registers 16, 17 to be executed by the associated system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.