Patent · US Expired

Process for the simultaneous production of self-aligned bipolar transistors and complementary MOS transistors on a common silicon substrate

US4737472A · kind A · utility

41Cited by
1References
15Claims
0Family size

Assignee

Inventors

Key dates

Filing dateNov 17, 1986
Grant dateApr 12, 1988
Priority date
Expiry dateNov 17, 2006

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY10S148/124

Abstract

A process for the simultaneous production of self-aligned bipolar transistors and complementary MOS transistors on a common silicon substrate wherein n-doped zones are produced in the p-doped substrate and insulated npn-bipolar transistors are formed into the n-doped zones. The n-zones form the collectors of the transistors and are modified according to conventional technology by additional process steps such that bipolar transistors are formed which are self-aligning both between the emitter and the base and also between the base and collector with extremely low-ohmic base terminals consisting of polysilicon and a silicide. Storage capacitances can also additionally be integrated into the structure. The use of the base terminals thus produced permits very small lateral emitter-collector distances. The combination of dynamic CMOS memory cells with fast bipolar transistors is made possible by the integration of the storage capacitances. The process is used for the production of VLSI circuits of high switching speeds.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.