Method for gate electrode fabrication and symmetrical and non-symmetrical self-aligned inlay transistors made therefrom
US4737828A · kind A · utility
26Cited by
9References
28Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 17, 1986 |
| Grant date | Apr 12, 1988 |
| Priority date | — |
| Expiry date | Mar 17, 2006 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An edge defining method is employed in the fabrication of narrow electrical patterns for VLSI circuits. The method is particularly employable in the formation of inlay MOSFET transistors having extremely narrow gate widths. The method is also particularly amenable to the fabrication of both symmetrical and non-symmetrical MOSFET devices on the same VLSI circuit chip. The inlay transistor structure is also employed to fabricate NOR and NAND type "ladder" networks and to join vertically and horizontally adjacent semiconductor devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.