VLSI integrated circuit having parallel bonding areas
US4737836A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 1986 |
| Grant date | Apr 12, 1988 |
| Priority date | — |
| Expiry date | Mar 18, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A very large scale multicell integrated circuit is provided with significantly improved circuit density. Both active and passive circuit elements are formed in a semiconductor substrate using ordinary diffusion techniques. Connectors, preferably made of polysilicon material, are then formed on the surface of the substrate. The connectors have bonding pad areas located along predetermined lines where metal connectors of later-formed metallization layers can be located. Some of the connectors have bonding pad areas connected to circuit elements while others are left unconnected. The subsequently formed metallization layers can then be used to connect together various ones of the circuit elements and multiple ones of the cells together in any desired circuit configuration using the polysilicon connectors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.