Process for producing an active matrix display screen with gate resistance
US4738749A · kind A · utility
27Cited by
3References
4Claims
0Family size
Inventors
Key dates
| Filing date | Jan 27, 1987 |
| Grant date | Apr 19, 1988 |
| Priority date | — |
| Expiry date | Jan 27, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2202/103
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Process for producing an active matrix display screen with gate resistance. A resistive layer, for example of aSi:n.sup.+ is inserted under the gate of the transistors. A short circuit in the insulating layer no longer risks short-circuiting a line and a column. Application to display.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.