Patent · US Expired

Integrated circuit structure for a quality check of a semiconductor substrate wafer

US4739388A · kind A · utility

9Cited by

7References

8Claims

0Family size

Assignees

Siemens Aktiengesellschaft · DE
U.S. Philips Corporation · US

Inventors

Gerhard Packeiser · Tauberbischofsheim, DE
Helmut Schink · Munich, DE
Gerard Martin · La Garenne-Colombes, FR
Jose Maluenda · Étampes, FR

Key dates

Filing date	Aug 27, 1986
Grant date	Apr 19, 1988
Priority date	—
Expiry date	Aug 27, 2006

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/3011
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An integrated circuit structure to be built on a semiconductor substrate wafer for the purpose of undertaking a quality check of the wafer has a plurality of field effect transistors laterally disposed in the same close adjacency as transistors which are to be manufactured on a chip using the wafer material. Each field effect transistor has its own well structure, its own source structure, and its own drain structure. The individual field effect transistors have pads allocated thereto at an edge of the structure. Each transistor source/drain structure is connected to the pads by a conductor, the totality of these conductors having width and/or length dimensions so that each run has approximately the same resistance. Only one common gate conductor for all of the transistors is provided.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.