Dynamic ram having folded bit line structure
US4739500A · kind A · utility
14Cited by
3References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 13, 1987 |
| Grant date | Apr 19, 1988 |
| Priority date | — |
| Expiry date | Feb 13, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic RAM comprises a sense amplifier and a restore circuit for each pair of divided bit lines. Sense operation can be performed in a fast and stable manner and the gate voltage of a transfer gate transistor need not be boosted over the power supply potential, so that the access time of the dynamic RAM can be reduced, operation margin thereof is increased, and reliability is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.