Fine tuning of atomic frequency standards
US4740761A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1986 |
| Grant date | Apr 26, 1988 |
| Priority date | — |
| Expiry date | Dec 23, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/26
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A predetermined bias voltage is applied to the input of a summing integrator in a frequency lock loop to provide fine tuning control of a voltage controlled crystal oscillator. In this arrangement, the predetermined bias voltage is summed and integrated with a phase error signal to alter the output frequency of the voltage controlled crystal oscillator. Since the servo loop operates to null the net voltage at the input of the integrator, the circuit induces a frequency error which just compensates for the intentional voltage offset bias applied to the integrator. The offset bias arrangement produces incremental offsets within a total range of about three parts in ten to the eleventh power and permits the output frequency of an atomic frequency standard to be accurately and stably adjusted in small increments to agree closely with the frequency of a national standard or other system reference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.