Full adder circuit using differential transistor pairs
US4740907A · kind A · utility
12Cited by
7References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 26, 1985 |
| Grant date | Apr 26, 1988 |
| Priority date | — |
| Expiry date | Mar 26, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high-speed full adder circuit comprising a plurality of differential transistor pairs and operating at multiple logic levels. This full adder can be made up of basic logic circuits, each having differential transistor pairs, such as exclusive-OR circuits, AND circuits and OR circuits. To reduce the chip size of the full adder, while ensuring a high-speed operation, transistors which may be used in common are replaced by a smaller number of transistors, thereby reducing the number of required transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.