Memory circuit and method of controlling the same
US4740923A · kind A · utility
19Cited by
1References
9Claims
0Family size
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Key dates
| Filing date | Nov 19, 1985 |
| Grant date | Apr 26, 1988 |
| Priority date | — |
| Expiry date | Nov 19, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K13/082
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A memory circuit is divided into a plurality of memory blocks, and an address register and a delay register are disposed in each memory block. Therefore, a read or write operation and a shifting operation of the address for storing data inside a memory matrix can be realized by a pipeline technique, and hence a memory circuit having a high processing speed is obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.