High-speed programmable divide-by-N counter
US4741004A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 29, 1986 |
| Grant date | Apr 26, 1988 |
| Priority date | — |
| Expiry date | Sep 29, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/665
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable divide-by-N counter employs a plurality of speed enhancement techniques to provide an overall operational speed corresponding to the speed at which a single-clocked flip-flop is capable of being toggled. The counter configuration provides flexibility in selecting the value of N, the programmable divisor, as well as the possibility of increasing the length the counting chain without producing a reduction in overall operational speed. The speed enhancement techniques are primarily located in the reset logic portion of the counter. A key aspect utilized through-out the overall circuit is that critical signal propagation paths in terms of speed of operation present no more than four gate delay intervals in total response time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.