Instruction prefetch system for conditional branch instruction for central processor unit
US4742451A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 1984 |
| Grant date | May 3, 1988 |
| Priority date | — |
| Expiry date | May 21, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A central processor unit for a digital data processing system that processes prefetched instructions including a conditional branch instruction. The processor includes a fetch unit that has separate portions, one that retrieves operands and the other that retrieves instructions. When the fetch unit fetches a conditional branch instruction, it may continue to prefetch "branch not taken" instructions using the instruction fetch portion. The fetch unit initially uses the operand fetch portion to prefetch "branch taken" instructions. If it is determined that the branch is not taken, the prefetch operation is aborted, otherwise the prefetch operation is allowed to continue to provide the next instruction used by the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.