Variable access frame buffer memory
US4742474A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 5, 1985 |
| Grant date | May 3, 1988 |
| Priority date | — |
| Expiry date | Apr 5, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/393
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A frame buffer memory comprises a set of memory chips arranged in an array of n rows (planes) and m columns. All memory chips are identically addressed, a set of m, n-bit pixels being stored at each memory address with one bit of each pixel being stored in each array plane. Each memory chip of each column is row address strobed by a common row address strobe line while each memory chip of each plane is column address strobed by a common column address strobe line. By appropriately strobing selected row and column address lines, data may be written to the memory array on a pixel-by-pixel or plane-by-plane basis with such data being written to individual pixels or planes or to blocks of pixels or planes. Combinational logic within the frame buffer memory permits pixel data to be rapidly modified according to preselected rules during a memory write operation prior to being written into memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.