ALU operation: modulo two sum
US4742520A · kind A · utility
9Cited by
14References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 1984 |
| Grant date | May 3, 1988 |
| Priority date | — |
| Expiry date | Sep 26, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for use in conjunction with the ALUs of computers, mini-computers, micro-computers and microprocessors wherein, upon a predetermined single command, the ALUs will be arranged to operate in a parity check mode or as a mask without otherwise disturbing the normal circuit operation of the ALUs utilized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.