Dynamic semiconductor memory device having a simultaneous test function for divided memory cell blocks
US4744061A · kind A · utility
63Cited by
2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 20, 1984 |
| Grant date | May 10, 1988 |
| Priority date | — |
| Expiry date | Nov 20, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic semiconductor memory device including memory cells divided into a plurality of blocks (1-1, 1-2). A simultaneous write enable circuit performs a write operation simultaneously upon the plurality of blocks, and a comparison circuit compares read data of one block with read data of the other block, thereby carrying out a test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.