Method of making a self-aligned MESFET using a substitutional gate with side walls
US4745082A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 12, 1986 |
| Grant date | May 17, 1988 |
| Priority date | — |
| Expiry date | Jun 12, 2006 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/14
Abstract
A process for producing a semiconductor device includes depositing a layer of insulator material onto a supporting substrate of the type having a surface which includes a channel region below the surface thereof containing a carrier concentration of a desired conductivity type, removing selected portions of the insulator material to form a substitutional gate on the substrate surface, forming side walls bounding substitutional gate to define an effective masking area in cooperation with the substitutional gate, ion implanting a dopant into the unmasked region of the substrate, removing the side walls, annealing the resultant device, removing the substitutional gate, depositing gate metal and first and second ohmic contacts in correct positional relation to one another on the substrate, and depositing metallic interconnects in electrical communication with the ohmic contacts to produce a semiconductor device. This technique is especially useful in the production of Group III-V compound semiconductors, particularly gallium arsenide semiconductors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.