Memory organization apparatus and method
US4745407A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 30, 1985 |
| Grant date | May 17, 1988 |
| Priority date | — |
| Expiry date | Oct 30, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/395
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An improved memory organization for use in a computer display system including a display having a plurality of display pixels for defining images that includes: a frame buffer memory having a plurality of memory cells organized into a matrix, said memory comprising first and second maps wherein the contents of the maps correspond to the pixels and define characteristics of the pixels, the maps being defined along X and Z axes of the matric; reading means coupled to the frame buffer memory for selectively reading, in one memory cycle operation, a plurality of bits from memory cells defining one of the maps; writing means coupled to said frame buffer memory for selectively storing, in one memory cycle operation, a plurality of bits into memory cells defining one of the maps; control logic means coupled to the reading means and the writing means for generating control signals for selectively reading a plurality of bits from one of the maps and writing a plurality of bits into one of the maps to define the images to be displayed on said display; wherein multiple maps may be defined in an array of memory cells, each of the maps providing different characteristics for the pixels of the d…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.