Semiconductor devices having compensated buffer layers

US4745448A · kind A · utility

Assignee

• Raytheon Company · US

Inventors

• H. Barteld Van Rees · Needham, US
• Barry J. Liles · Westborough, US

Key dates

• Filing date: Dec 24, 1985
• Grant date: May 17, 1988
• Expiry date: Dec 24, 2005

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/854

Abstract

A field effect transistor includes a substrate of gallium arsenide having a resistivity of at least about 10.sup.7 ohm/cm and a first buffer layer of gallium arsenide disposed over the substrate having a deep level acceptor dopant incorporated into the buffer layer to compensate for donor dopants incorporated into the buffer layer. The concentration of the donor dopants and the acceptor dopant are controlled to provide the buffer layer with a predetermined resistivity characteristic of about 10.sup.7 -10.sup.8 ohm/cm. The concentration of the deep acceptor dopant is substantially constant at about 10.sup.16 acceptors/cc throughout the first buffer layer. The buffer layer preferably has a thickness of at least 2 microns and preferably between 5 and 30 microns. A second buffer layer is disposed over the first buffer layer having a monotonically declining concentration of chromium dopant from about 10.sup.16 to less than about 10.sup.14 acceptors/cc. An active layer and contact layer of suitably n-type doped gallium arsenide are consecutively disposed over at least portions of the second buffer layer.