Equalizer for digital transmission systems
US4745622A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 29, 1986 |
| Grant date | May 17, 1988 |
| Priority date | — |
| Expiry date | Jul 29, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B3/145
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A post-equalizer and pre-equalizer circuit for use in communicating between nodes in a Pulse Amplitude Modulated (PAM) digital or analog communication system is described. The post-equalizer circuit comprises a first variable zero circuit, a second variable zero circuit, and a gain shaper circuit wherein the gain and frequency location of the zeros in the zero circuits combined with the gain of the gain shaping circuit are simultaneously controlled by a control circuit which generates a control voltage which is a monotonically increasing function of cable loss. In the case of a PAM digital communication system, the control voltage generates a signal equal to the difference between the equalized signal and the original transmitted signal which is used to vary the resistance of voltage variable resistors in the form of FET's in each of the zero circuits and gain shaper circuits. In the case of an analog system, the control voltage is derived from the sealing current that is determined by the DC resistance of the cable to be equalized. If the cable loss is above a predetermined value, a pre-equalizer circuit is switched into the transmit path of the communication system and provides a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.