Method for reducing effects of electrical noise in an analog-to-digital converter
US4746899A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1986 |
| Grant date | May 24, 1988 |
| Priority date | — |
| Expiry date | Oct 7, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/458
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Method for reducing deleterious effects of electrical noise in an analog-to-digital converter wherein both the analog and digital circuitry of the A/D converter are embodied in the same integrated circuit. The method includes sampling an analog input voltage with a first clock signal, generating a second clock signal that is delayed with respect to the first clock signal, and using the second clock signal as a clock for the digital circuitry. In accordance with another aspect of the invention, the method for reducing effects of noise in an A/D converter wherein such noise is generated by a digital decimation filter includes synchronously pipelining the arithmetic operations of the digital decimation filter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.