Device for improving detection of unoperational states in non-attended driven processor
US4748587A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 1985 |
| Grant date | May 31, 1988 |
| Priority date | — |
| Expiry date | Nov 25, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0757
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Device for detecting the unoperational states of an interrupt driven processor executing instructions on n priority levels, n-1 being the lowest priority level and 0 the highest priority level. It comprises means (18) for dispatching the unoperational state detection task running on the n-1 priority level at time intervals smaller than a specified time-out delay. A detection timer (1) is set at an initial value each time the task is dispatched and the content is changed stepwise once the task has been dispatched and an interval timer (13) having a minimum step value. Means (20) are responsive to the final value taken by the detection timer when the time-out delay has elapsed, to send a level 0 interrupt to the processor. A REMEMBER LATCH (26) is set at the occurrence of the first next pulse from the interval timer if the detection timer is at its final value and is reset when the level 0 interrupt handling succeeds in restoring the cause of said level 0 interrupt request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.