System for determining occurrence sequence of sampled data
US4748624A · kind A · utility
1Cited by
10References
4Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 18, 1986 |
| Grant date | May 31, 1988 |
| Priority date | — |
| Expiry date | Jun 18, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3177
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In a logic analyzer including first and second sampling channels operative with different clocks independently, a system for determining sequence in time in which the sampled data are generated in both sampling channels includes a memory interposed between the first and second sampling channels. The memory has a data input supplied with the address data of the first sampling channel, an address input supplied with the address data of the second sampling channel and a data write input supplied with the clock signal of the second sampling channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.